Solid-state electronic memories are used widely across many hardware platforms, including embedded systems, mobile devices, desktop computers, and servers. Such memories can be classified in different ways, such as according to whether such memories are “volatile” or “non-volatile.” Generally, non-volatile memories can reliably retain state after removal of input power. Conversely, volatile memories generally retain their state only when powered. In particular, volatile memories can be sub-classified as either static or dynamic. A static memory generally retains its state indefinitely when powered. By contrast, a dynamic memory may slowly lose its state, such as due to leakage of a storage structure within the dynamic memory. Accordingly, dynamic memories are generally “refreshed” in a manner where the state of the memory is read and then written back to the storage structure in order to preserve state.
Despite the inconvenience of refresh, dynamic random access memories (DRAM) have achieved tremendous adoption due to the ability to fabricate extremely dense arrays of such memories using relatively simple memory cell structures. For example, a single bit DRAM cell can be fabricated using as little as a single transistor and a single storage structure (e.g., a capacitor). FIG. 1A illustrates a simple schematic representation of a one-transistor one-capacitor (1T-1C) DRAM cell 100A. FIGS. 1B, 1C, 1D, 1E, 1F, and 1G illustrate generally a variety of 1T-1C DRAM structures 100B, 100C, 100D, 100E, 100F, and 100G that can be fabricated using semiconductor processing techniques, such as using a silicon complementary-metal-oxide-semiconductor (CMOS) process. FIGS. 1A through 1G can each include a bit line (BL) node 108, a word line (WL) node 106, a storage node 102, and a plate node 104. As transistor geometries have shrunk, area inefficient planar capacitor structures, such as shown in FIG. 1B, have given way to a variety of other capacitor geometries. Such geometries include more efficient stacked configurations (e.g., FIG. 1C), horizontally-finned or concentric cylindrical structures (e.g., FIGS. 1D and 1E), or trenched configurations (e.g., FIGS. 1F and 1G).
FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate generally a series of fabrication operations 200A, 200B, 200C, 200D, 200E, and 200F that can be used to provide a concentric cylindrical capacitor configuration, such as similar to FIG. 1E. While the configurations shown in FIGS. 1B through 1G and FIGS. 2A through 2F have increased area efficiency as compared to first-generation planar structures, scaling limits may exist. Such capacitor structures have also been enhanced by inclusion of a high-relative-dielectric-constant (e.g., “high-K”) material, such as a film, as a portion of a plate of the capacitor structure. Such materials can include Ta2O5, Al2O3, or HfO2. Such techniques have enabled single-die DRAM devices to achieve densities providing a gigabit (e.g., about 109 bits) of storage in a single device.
By contrast, FIG. 3 illustrates a schematic representation of a six-transistor (6T) static random access memory (SRAM) cell 300. Such an SRAM cell 300 can offer advantages of low latency, and a lack of requiring refresh (e.g., SRAM can be referred to as “refresh-free”), but at a cost of significantly higher bit-cell complexity. In FIG. 3, transistors M1, M2, M3, and M4 can provide a cross-coupled inverter pair configuration. Transistors M6 and M5 can be controlled using a word line (WL), such as to couple the cross-coupled inverter pairs to a bit line (BL) and an inverted bit line (e.g., BL Bar or “BLB”).